|
組別 :碩士在職專班
5月26日
09:00~10:40
|
地 點 :
聖言樓一樓大廳
|
|
論
文
題
目
|
原
發
表
處
|
|
|
Using an FPGA Chip to
Design a Highspeed Control System for Multiple Sets of Programmable DC
Electronic Loads
白英文、郭肇勳
|
The Sixth IASTED International Conference
on Communications, Internet, and Information Technology (CIIT 2007), Banff,
Alberta, Canada.
|
113 |
|
|
|
|
|
最簡化U-NII Band之 5.2 GHz WLAN CMOS
低雜訊放大器設計
林昇洲、謝祥界
|
第五屆現代通訊科技應用學術研討會， 96.03.16，北台科灣學技術學院。
|
119 |
|
|
|
|
|
組別 :
碩士班
5月26日
09:00~10:40
|
地 點 :
聖言樓一樓大廳
|
|
論
文
題
目
|
原
發
表
處
|
|
|
雜訊干擾對寬頻電力線通訊系統之通訊品質分析
李永勳、古書瑋、蕭松欣、劉季安
|
第二十七屆電力工程研討會論文集第五冊，92.12.22，新竹清華大學，OE
6.5.1~6.5.6 頁。
|
124 |
|
|
|
|
|
Performance
and Power Consumption of Computers using Batch Service with Event and Time
Counter
Ying-Wen Bai, Yung-Sen Cheng
|
Proceedings of the IASTED International Conference on
Parallel and Distributed Computing and Networks (PDCN 2007), Innsbruck,
Austria, Feb. 13-15, 2007, pp. 133-138.
|
131 |
|
|
|
|
|
Design and
Implementation of an Embedded Home-Gateway for Remote Monitoring Based on
OSGi Technology
Ying-Wen Bai, Jui-Po Hsu
|
Proceedings of the IASTED European
Conference on Internet and Multimedia Systems and Applications (EuroIMSA
2007),
Chamonix, France, March 14-16, 2007, pp. 63-68.
|
137 |
|
|
|
|
|
|
|
|
|
Adjusting
Clock Rates in a PDA System to Reduce the Jitter Through Wireless VOIP
Ying-Wen Bai, Yung-De Cheng
|
Accepted by the Sixth IASTED International Conference on
Communications, Internet, and
Information Technology (CIIT 2007), Banff, Alberta, Canada, April 2, 2007.
|
143 |
|
|
|
|
|
|
|
|
|
Semi-Blind Channel Estimation with Linear Smoothing Scheme for SIMOOFDM
Systems without Cyclic Prefix
Jung-Lang Yu, Chia-Hao Chen, Mei-Chen Lee
|
Proceedings of 2006 International Symposium on
Communications，Taiwan，R.O.C，November 2006.
|
149 |
|
|
|
|
|
|
|
|
|
Blind Channel Estimation for MC-CDMA MIMO Systems with 4-Tx Space-Time Block
Codes
Jung-Lang Yu, Ming-Feng Lee, Zhi-Yuan Shi
|
Proceedings of 2006 International Symposium on
Communications. ， Taiwan, R.O.C，November 2006.
|
155 |
|
|
|
|
|
Overcoming Glitches and Dissipation Timing Skews in Design of DPAResistant
Cryptographic Hardware
Kuan Jen Lin, Shih Hsien
Yang, Shan Chien Fang, Cheng Chia Lo
|
Accepted by IEEE/ACM DATE,
Nice, 2007.
|
161 |
|
|
|
|