Duo Sheng

Associate Professor

Tel: +886-2-29053800

Fax:+886-2-29042638

Email:duosheng@mail.fju.edu.tw

Office:

SF707,

Department of Electrical Engineering,

Fu Jen Catholic University ,

510, Zhongzheng Rd., Xinzhuang Dist., New Taipei City 24205, Taiwan, ROC

 

 

 

Educations:

2003/9 ~ 2010/6: Ph.D., Electronics Engineering, National Chiao Tung University

1997/9 ~ 1999/6: M.S., Electrical Engineering, National Chung Cheng University

1993/9 ~ 1997/6: B.S., Electrical Engineering, National Chung Cheng University

Professional Experience:

2016/02 ~ Present: Associate Professor, Department of Electrical Engineering,

Fu Jen Catholic University ,

2010/09 ~ 2016/01: Assistant Professor, Department of Electrical Engineering,

Fu Jen Catholic University ,

2010/03 ~ 2010/07: Senior Engineer, Sunplus(凌陽科技)

2007/01 ~ 2009/09: Project Manager, KeyASIC(佳易科技)

1999/10 ~ 2006/12: Consultant Engineer, Macronix(旺宏電子)

Research Interests:

l   Low-Power and System-on-a-Chip (SoC) Design Technology

l   All-Digital Clock Generator Design

l   High-Speed Serial Link Interface

l   Biomedical IC Design

Laboratory:

VLSI/CAD Laboratory (SF741)

Courses:

l   Digital Design

l   Logic Lab.

l   Hardware Description Language

l   Introduction to Digital Chip Design

l   Low-Power IC Design

l   Nanometer IC Design

Projects:

1.        Study of digitally controlled oscillator and all-digital spread-spectrum clock generator design, NSC 100-2218-E-030-001-, 2011/01/01 ~ 2011/10/31

2.        Study of PVT tolerant all-digital clock generator for SoC applications, NSC 100-2221-E-030-012-, 2011/08/01 ~ 2012/07/31

3.        Study of an all-digital reference clock generator for WBAN applications, NSC 101-2221-E-030 -025-, 2012/08/01 ~ 2013/07/31

4.        智慧電子整合性人才培育計畫 - 生醫影像處理系統,教育部顧問室, 2011/09/01 ~ 2016/01/31

5.        Study of an all-digital UWB pulse generator for wireless biotelemetry applications  - 輔仁大學理工學院, 2014/02/01 ~ 2014/07/15

6.        Study of an all-digital and high-resolution transmit beamformer for high-frequency ultrasonic imaging system applications, MOST 103-2221-E-030 -025 -, 2014/08/01 ~ 2015/07/31

7.        Study of critical digital integrated circuit of positron emission tomography detector, MOST 104-2221-E-030-019-, 2015/08/01 ~ 2016/07/31

8.        Study of an all-digital and high-resolution transmit beamformer for high-frequency ultrasonic imaging system applications - 輔仁大學理工學院, 2015/10/01 ~ 2016/06/15

9.        Study of digital multi-channel readout circuit for high-resolution Micro-PET detector applications, MOST 105-2221-E-030-017-, 2016/08/01 ~2017/07/31

10.    Study of an all-digital and low-complexity dynamic focusing transmit beamformer for high-frequency ultrasonic imaging system applications - 輔仁大學理工學院, 2016/11/01~2017/06/15

Publications:

l   Referred Journal Articles

1.        Duo Sheng and Yu-Chan Hung, “Wide-range and high-resolution on-chip delay measurement circuit with low supply-voltage sensitivity for SoC applications,” Review of Scientific Instruments, vol. 87, Nov. 2016.

2.        Duo Sheng and Min-Rong Hong, “A low-power all-digital on-chip CMOS oscillator for a wireless sensor node,” Sensors, vol. 16, Oct. 2016.

3.        Ching-Che Chung, Duo Sheng, and Chang-Jun Li, “A wide-range low-cost all-digital duty-cycle corrector,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2487-2496, Nov. 2015.

4.        Ching-Che Chung, Duo Sheng, and Wei-Da Ho, “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983-987, May. 2015.

5.        Duo Sheng, Hsiu-Fan Lai, Sheng-Min Chan and Min-Rong Hong, “A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems,” Sensors, vol. 15, pp. 4408-4424, Feb. 2015.

6.        Ching-Che Chung, Duo Sheng, and Sung-En Shen, High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1096-1105, May. 2014.

7.        Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, and Shu-Syun Jhao, High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications,IEICE Electronics Express (ELEX) , vol. 11, no. 3, Jan. 2014.

8.        Ching-Che Chung, Duo Sheng, and Wei-Da Ho, A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS,IEICE Electronics Express (ELEX), vol. 10, no. 6, Mar. 2013.

9.        Ching-Che Chung, Duo Sheng, and Ning-Mi Hsueh, A high-performance wear-leveling algorithm for flash memory system,IEICE Electronics Express (ELEX), vol. 9, no. 24, pp. 1874-1880, Dec. 2012.

10.    Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, and Fang-Nien Lu, An all-digital large-N audio frequency synthesizer for HDMI applications,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 7, pp. 424-428, Jul. 2012.

11.    Duo Sheng, Ching-Che Chung, Jhih-Ci Lan, and Hsiou-Fan Lai, Monotonic and low-power digitally controlled oscillator with portability for SoC applications,Electronics Letters, vol. 48, no. 6, pp. 321-323, Mar. 2012.

12.    Ching-Che Chung, Duo Sheng, and Sung-En Shen, A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology,IEICE Electronics Express (ELEX), vol. 8, no. 15, pp. 1245-1251, Aug. 2011.

13.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113-1117, Jun. 2011.

14.    Ching-Che Chung, Duo Sheng, and Chia-Lin Chang, A 600 kHz to 1.2 GHz all-digital delay-locked loop in 65nm CMOS technology,IEICE Electronics Express (ELEX), vol. 8, no. 7, pp. 518-524, Apr. 2011.

15.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “Wide Duty Cycle Range Synchronous Mirror Delay Designs,” Electronics Letters, vol. 46, no.5, pp. 338-340, Mar. 2010.

16.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “Fast-Lock All-Digital DLL and Digitally-Controlled Phase Shifter for DDR Controller Applications,” IEICE Electronics Express, vol. 7, no.9, pp. 634-639, May 2010.

17.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007.

18.    Jinn-Shyan Wang, Po-Hui Yang, and Duo Sheng, Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 583–592, Apr. 2000.

 

 

l   Conference Proceedings

1.        Duo Sheng, Chia-Lin Wu, Yu-Chan Hung, and Yi-Shang Wang, “All-digital and low-power reference clock generator for biotelemetry applications,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jul. 2016.

2.        Duo Sheng, Chih-Chung Huang, Zong-Ru Yang, and Yi-Shang Wang, “An all-digital and high-resolution transmit beamforming ASIC for high-frequency and portable ultrasonic imaging systems,” IEEE International Ultrasonics Symposium, Oct. 2015. 

3.        Duo Sheng, Ching-Che Chung, Chia-Lin Wu, Sheng-Min Chan, and Min-Rong Hong, “An all-digital and wide-range reference clock generator for biotelemetry applications,” International Conference on Electronics and Software Science (ICESS), Jul. 2015.

4.        Ching-Che Chung, Duo Sheng, and Chen-Han Chen, An all-digital phase-locked loop compiler with liberty timing files,in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014.

5.        Duo Sheng, Ching-Che Chung, Chih-Chung Huang, and Jia-Wei Jian, A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications,35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Jul. 2013.

6.        Duo Sheng and Zong-Ru Yang, A Low-Energy and All-Digital Pulse Generator of IR-UWB Transmitter for Capsule Endoscope,35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Jul. 2013.

7.        Ching-Che Chung, Duo Sheng, and Wei-Siang Su, A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices,in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013.

8.        Duo Sheng, Ching-Che Chung, and Jhih-Ci Lan, A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications,in Proceedings of IEEE 4th Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012.

9.        Ching-Che Chung, Duo Sheng, and Yang-Di Lin, An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology,in Proceedings of IEEE 4thAsia Symposium on Quality Electronic Design (ASQED), Jul. 2012.

10.    Ching-Che Chung, Duo Sheng, and Wei-Da Ho, A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012

11.    Duo Sheng, and Jhih-Ci Lan,A Monotonic and Low-Power Digitally Controlled Oscillator with Portability for SoC Applications,” Proceedings of the 54th IEEE Midwest Symposium on Circuits and Systems, Aug. 2011.

12.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An All Digital Spread Spectrum Clock Generator with Programmable Spread Ratio for SoC Applications,” in Proc. 2008 IEEE Asia Pacific Conf. on Circuits and Systems, Nov. 2008, pp. 850–853.

13.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications,” in Proc. 2006IEEE VLSI-DAT, Apr. 2006, pp. 207-210.

14.    Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications,” in Proc. 2006 IEEE Asia Pacific Conf. on Circuits and Systems, Dec. 2006, pp. 105–108.

15.    Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, and Yu-Ming Huang, A compact adaptive equalizer IC for HIPERLAN system,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 265-268, May 2000.

Patents:

1.        Duo Sheng, Min Nan Yen, Ken Liou, “Re-programmable logic array,” US Patent No. 6693453, 2004.

2.        Min Nan Yen and Duo Sheng, “Memory device having built-in error-correction capabilities,” US Patent No. 7079430, 2006.

3.        Min Nan Yen, Duo Sheng, Shou-Chang Tsai, Koug Mou LiouDigital phase-locked loop compiler,” US Patent No. 7145975, 2006.

4.        嚴敏男,盛鐸,蔡壽昌,劉康懋,數位式鎖相迴路中華民國專利發明第I245491號,94年。

5.        嚴敏男,盛鐸具有內建錯誤糾正能力之記憶體元件中華民國專利發明第I301975號,97年。

Services:

l   Paper Reviewer

n   IEEE Transactions on Circuits and Systems I (TCAS-I)

n   IEEE Transactions on Circuits and Systems II (TCAS-II)

n   IEEE Transactions on Instrumentation & Measurement

n   Sensors

n   Microelectronics Journal

n   IEICE Electronics Express

n   Integration the VLSI Journal

n   IEEE Symposium on VLSI Circuit

n   IEEE International Symposium on Circuits & Systems